Electronic industry development has been faithful to Moore's law as devices are becoming smaller and the number of transistors larger. For example, in 1980, INTEL's 8086 had about 50,000 transistors; in 1990, 486 had about 1,000,000 transistors; in 2000, PENTIUM4 had about 50,000,000 transistors; and in 2010, SIX-CORE 17 had about 1,000,000,000 transistors. There are two significant challenges with this ever-increasing transistor count. First, a central challenge of the electronic industry is power consumption of integrated circuits which are now composed of billions of transistors. Second, as the channel length of transistors (e.g., metal oxide semiconductors field effect transistor, MOSFET) is becoming smaller and smaller in order to increase both the operation speed and the number of transistors per chip, a phenomenon referred to as a short channel effect (SCE) becomes prominent. SCE specifically becomes problematic when the channel length is of the same order of magnitude as the depletion-layer widths. SCE manifest itself in several ways including: a subthreshold voltage roll-off (Vt roll-off), a drain-induced barrier lowering (DIBL) and a source-drain punch through, thus increasing the inverse subthreshold slope of metal oxide semiconductor field effect transistor (MOSFET) and thereby significantly increasing off-state leakage current. Particularly, with off-state leakage as a measure of power performance, MOSFETs performance deteriorate progressively in submicron, deep submicron, and nano-scale channel lengths. Additionally, MOSFETs are fundamentally unable to have sharp ON-to-OFF transition, which implies that they need a relatively large operating voltage to supply the needed ON current to operate. Furthermore, the higher the desired operating speed (i.e. frequency of ON to OFF transitions), the higher the needed ON current and consequently the higher the supply voltage, hence the power consumption problem is further exacerbated. Accordingly, it is essential to reduce the power consumption in chips with large numbers of transistors especially those operating at high frequencies. Therefore, a main challenge in miniaturizing MOSFETs is scaling down the supply voltage VDD, as needed to reduce power. A smaller VDD can be achieved in a switch with sharper ON to OFF transition. However, the steepness of conventional MOSFETs have a fundamental limit due to thermionic injection of carriers over the channel barrier (60 mV/decade at room temperature). The cause of this limit is also referred to as a hot carrier leakage.
Devices known as tunnel field effect transistors (TFETs) have been introduced in an attempt to address these issues. The hot carrier leakage problem does not exist in the tunnel FETs, which work based on injection of cold carriers. The doping profile of TFETs is P-i-N, unlike MOSFETs which typically use an N-i-N or P-i-P profile. Hence, the bandgap of a TFET filters out the hot carriers. TFETs are able to provide steep ON-to-OFF transitions allowing them to operate at lower voltages and significantly reduce the power consumption. However, one challenge of conventional TFETs is that the tunneling transmission probability is small, which results in small ON current levels and low speed. Moreover, scaling the channel length below 10 nm in conventional TFETs is shown to be exceedingly challenging as further length scaling significantly degrades OFF-state of conventional TFETs. Given these challenges, the Moore's law appears to be at a dead-end.
Therefore, there is an unmet need for a novel TFET design that improves upon conventional TFET current performance both in the ON- and OFF-states.